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ltc3103 1 3103f typical application features description 1.8a quiescent current, 15v, 300ma synchronous step-down dc/dc converter the ltc ? 3103 is a high efficiency, monolithic synchronous step-down converter using a current mode architecture capable of supplying 300ma of output current. the ltc3103 offers two operational modes: automatic burst mode operation and forced continuous mode allow - ing the user the ability to optimize output voltage ripple, noise and light load efficiency. with burst mode operation enabled, the typical dc input supply current at no load drops to 1.8a maximizing the efficiency for light loads. selection of forced continuous mode provides very low noise constant frequency, 1.2mhz operation. additionally, the ltc3103 includes an accurate run com - parator, thermal overload protection, a power good output and an integrated soft-start feature to guarantee that the power system start-up is well controlled. applications n ultralow quiescent current: 1.8a n synchronous rectification: efficiency up to 95% n wide v in range: 2.5v to 15v n wide v out range: 0.6v to 13.8v n 300ma output current n user-selectable automatic burst mode ? or forced continuous operation n accurate and programmable run pin threshold n 1.2mhz fixed frequency pwm n internal compensation n power good status output for v out n available in thermally enhanced 3mm 3mm 0.75mm, 10-pin dfn and 10-pin msop packages n remote sensor networks n distributed power systems n multicell battery or supercap regulator n energy harvesters n portable instruments n low power wireless systems l , lt, ltc, ltm, burst mode, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. v in 0.022f bst 3v to 15v mode sw run pgood v cc fb ltc3103 gnd 665k 10h 2.2v 300ma 3103 ta01a 47f 1f 10f 1.78m 12pf efficiency vs output current output current (a) 65 efficiency (%) power loss (mw) 95 100 60 55 90 75 85 80 70 0.0001 0.01 0.1 1 3103 ta01b 50 0.1 1 10 100 0.001 v in = 3v v in = 5v v in = 10v v in = 15v
ltc3103 2 3103f absolute maximum ratings v in ............................................................. C0.3v to 18v sw ................................................ C0.3v to (v in + 0.3v) fb ................................................................ C0.3v to 6v bst ........................................ (sw C 0.3v) to (sw + 6v) run, mode ............................................... C0.3v to v in v cc , pgood ................................................. C0.3v to 6v (note 1) order information lead free finish tape and reel part marking* package description temperature range ltc3103edd#pbf ltc3103edd#trpbf lfxh 10-lead (3mm 3mm) plastic dfn C40c to 125c ltc3103idd#pbf ltc3103idd#trpbf lfxh 10-lead (3mm 3mm) plastic dfn C40c to 125c ltc3103emse#pbf ltc3103emse#trpbf ltfxj 10-lead plastic msop C40c to 125c ltc3103imse#pbf ltc3103imse#trpbf ltfxj 10-lead plastic msop C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ electrical characteristics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 10v unless otherwise noted. top view 11 gnd dd package 10-lead (3mm 3mm) plastic dfn 10 9 6 7 8 4 5 3 2 1 mode nc fb run v cc v in sw bst gnd pgood t jmax = 125c, ja = 58c/w, jc = 10c/w exposed pad (pin 11) is gnd, must be soldered to pcb 1 2 3 4 5 v in sw bst gnd pgood 10 9 8 7 6 mode nc fb run v cc top view 11 gnd mse package 10-lead plastic msop t jmax = 125c, ja = 40c/w, jc = 5.0c/w exposed pad (pin 11) is gnd, must be soldered to pcb pin configuration operating junction temperature range (notes 2, 3) ............................................ C40c to 125c storage temperature range .................. C65c to 150c lead temperature (soldering, 10 sec) mse only .......................................................... 300c parameter conditions min typ max units step-down converter input voltage range l 2.5 15 v input undervoltage lockout threshold v in rising v in rising, t j = 0c to 85c (note 4) l 2.1 2.1 2.6 2.5 v v input undervoltage lockout hysteresis (note 4) 0.4 v
ltc3103 3 3103f electrical characteristics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 10v unless otherwise noted. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3103 is tested under pulsed load conditions such that t j t a . the ltc3103e is guaranteed to meet specifications from 0c to 85c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3103i is guaranteed over the full C40c to 125c operating junction temperature range. the junction temperature (t j ) is calculated from the ambient temperature (t a ) and power dissipation (p d ) according to the formula: t j = t a + (p d )( ja c/w) where ja is the package thermal impedance. note the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. note 3: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. the maximum rated junction temperature will be exceeded when this protection is active. continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. note 4: specification is guaranteed by design. note 5: the ltc3103 has a proprietary test mode that allows testing in a feedback loop which servos v fb to the balance point for the error amplifier. parameter conditions min typ max units feedback voltage (note 5) l 0.588 0.6 0.612 v feedback voltage line regulation v in = 2.5v to 15v (note 5) 0.02 0.05 %/v feedback input current (note 5) l 1 20 na oscillator frequency t j = 0c to 85c (note 4) l 0.930 1 1.2 1.2 1.55 1.45 mhz mhz quiescent current, v in active run = v in , mode = 0v, fb > 0.612 nonswitching 600 a quiescent current, v in sleep run = v in , fb > 0.612, mode = v in , t j = 0c to 85c (note 4) run = v in , fb > 0.612, mode = v in l 1.8 1.8 2.6 3.3 a a quiescent current, v in shutdown run = 0v, t j = 0c to 85c (note 4) run = 0v l 1 1.8 1.7 3.3 a a n-channel mosfet synchronous rectifier leakage current v in = v sw = 15v, v run = 0v 0.01 0.3 a n-channel mosfet switch leakage current v in = 15v, v sw = 0v, v run = 0v 0.01 0.3 a n-channel mosfet synchronous rectifier r ds(on) i sw = 200ma 0.85 n-channel mosfet switch r ds(on) i sw = C200ma 0.65 peak current limit l 0.40 0.50 0.75 a pgood threshold fb falling, percentage below fb C14 C10 C5 % pgood hysteresis percentage of fb 2 % pgood voltage low i pgood = 100a 0.2 v pgood leakage current v pgood = 5v 0.01 0.3 a maximum duty cycle l 89 92 % switch minimum off time (t off(min) ) (note 4) 65 ns synchronous rectifier minimum on time (t on(min) ) (note 4) 70 ns run pin threshold run pin rising l 0.76 0.80 0.85 v run pin hysteresis 0.06 v run input current run = 1.2v l 0.01 0.4 a mode threshold l 0.5 0.8 1.2 v mode input current mode = 1.2v 0.1 4 a soft-start time 0.7 1.4 2.5 ms
ltc3103 4 3103f typical performance characteristics efficiency vs output current efficiency vs input voltage (automatic burst mode operation) application no-load input current vs supply voltage (automatic burst mode operation) t a = 25c unless otherwise noted output current (a) 65 efficiency (%) 95 100 60 55 90 75 85 80 70 0.0001 0.01 0.1 1 3103 g01 50 0.001 v in = 4v v in = 7v v in = 10v v in = 15v v out = 3.3v l = 15h input voltage (v) 2 efficiency (%) 95 8 3103 g02 80 70 4 6 10 65 50 60 55 100 90 85 75 12 14 16 v out = 2.2v l = 10h i load = 300ma i load = 100ma i load = 10ma i load = 1ma i load = 100a input voltage (v) 0 1.6 input current (a) 1.9 1.8 1.7 2.0 2.1 2.2 2 4 6 8 3103 g03 10 12 14 16 18 front page application efficiency vs output current (forced continuous operation) efficiency vs input voltage (forced continuous operation) feedback voltage vs temperature oscillator frequency vs temperature r ds(on) vs temperature application no-load input current vs supply voltage (forced continuous operation) output current (a) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.0001 0.01 0.1 1 3103 g04 0 0.001 v in = 3.7v v in = 5v v in = 7v v in = 10v v in = 15v v out = 3.3v l = 10h input voltage (v) 3 0 efficiency (%) 10 30 40 50 100 70 7 11 13 15 3103 g05 20 80 90 60 5 9 v out = 3.3v, l = 10h i load = 300ma i load = 100ma i load = 10ma i load = 1ma input voltage (v) 2 2.0 2.5 3.5 8 12 3103 g06 1.5 1.0 4 6 10 14 16 0.5 0 3.0 input current (ma) front page application ldo enabled temperature (c) ? 60 change in v fb (%) 0.25 0.50 0.75 100 3103 g07 0 ?0.25 ?0.50 ? 20? 40 200 60 80 120 40 140 normalized to 25c temperature (c) ?50 ?10 frequency change (%) ?8 ?4 ?2 0 10 4 0 50 75 3103 g08 ?6 6 8 2 ?25 25 100 125 150 normalized to 25c temperature (c) ?50 change in resistance (%) 40 25 3103 g09 10 ?10 ?25 0 50 ?20 ?30 50 30 20 0 75 100 125 normalized to 25c v in = 10v synchronous rectifier main switch
ltc3103 5 3103f typical performance characteristics t a = 25c unless otherwise noted application no-load input current vs temperature (automatic burst mode operation) sw leakage vs temperature peak current limit change vs temperature temperature (c) ?50 leakage current (na) 350 25 3103 g10 200 100 ?25 0 50 50 0 400 300 250 150 75 100 150125 v in = 10v main switch synchronous rectifier temperature (c) ?50 peak current limit change (%) ?2.5 0 2.5 40 100 3103 g11 ?5.0 ?7.5 ?10.0 ?20 10 70 5.0 7.5 10.0 130 temperature (c) ?50 input current (a) 2.2 2.6 110 3103 g12 1.8 1.6 1.0 ?10 30 70 ?30 10 50 90 3.0 2.0 2.4 1.4 1.2 2.8 v in = 10v v out = 2.5v automatic burst mode operation forced continuous operation start-up into pre-biased output (automatic burst mode operation) start-up into pre-biased output (forced continuous operation) start-up from shutdown (automatic burst mode operation) v out 50mv/div ac-coupled i l 100ma/div 10s/div 3103 g13 i load = 25ma v in = 10v c in = 10f l = 10h v out = 2.5v c out = 22f v out 20mv/div ac-coupled i l 100ma/div 1s/div 3103 g14 i load = 25ma v in = 10v c in = 10f l = 10h v out = 2.5v c out = 22f run 5v/div v out 1v/div pgood 5v/div i l 100ma/div 500s/div 3103 g15 i load = 2ma v in = 10v c in = 10f l = 10h v out = 2.5v c out = 47f burst current pulses soft-start period v bst refresh current pulses run 5v/div v out 1v/div i l 100ma/div pgood 5v/div 500s/div 3103 g16 i load = 2ma v in = 10v l = 10h v out = 2.5v v bst refresh current pulses run 5v/div pgood 5v/div v out 1v/div i l 100ma/div 500s/div 3103 g17 i load = 25ma v in = 10v l = 10h v out = 2.5v start-up from shutdown (forced continuous operation) run 5v/div v out 1v/div i l 100ma/div 500s/div 3103 g18 i load = 5ma v in = 10v l = 10h v out = 2.5v soft-start foldback period
ltc3103 6 3103f typical performance characteristics t a = 25c unless otherwise noted automatic burst mode threshold vs supply voltage load step (automatic burst mode operation) load step (forced continuous operation) load regulation (automatic burst mode operation) load regulation (automatic burst mode operation) load regulation (automatic burst mode operation) maximum duty cycle vs input voltage minimum input voltage at maximum duty cycle vs load current minimum input voltage at maximum duty cycle vs load current v out 200mv/div ac-coupled i l 200ma/div i load 200ma/div 200s/div 3103 g19 i load = load step, 5ma to 300ma v in = 10v c in = 10f l = 10h v out = 2.2v c out = 47f v out 50mv/div ac-coupled i l 100ma/div i load 100ma/div 200s/div 3103 g20 i load = load step, 50ma to 200ma v in = 10v l = 10h v out = 2.5v c out = 22f input voltage (v) 0 0 burst threshold (i load , ma) 20 60 80 100 140 4 8 10 3103 g27 40 160 120 2 6 12 14 16 v out = 1.2v v out = 1.8v v out = 2.5v v out = 3.3v v out = 5v load current (ma) 0 2.5 input voltage (v) 3.0 3.5 4.0 4.5 5.5 50 100 150 200 3103 g21 250 300 5.0 v out = 4.2v v out = 3.3v v out = 2.5v v out = 2.2v v out = 1.8v v out = 1.5v load current (ma) 0 5 input voltage (v) 7 9 11 50 100 150 200 3103 g22 250 13 15 6 8 10 12 14 300 v out = 12v v out = 9v v out = 5v i load (ma) 0 ?2.0 change in v out (%) ?1.5 ?1.0 ?0.5 0 0.5 1.0 10 20 30 40 3103 g23 50 normalized at i load = 100ma v in = 10v v out = 5v c ff = 12pf c out = 68f c out = 47f c out = 22f i load (ma) 0 ?2.0 change in v out (%) ?1.5 ?1.0 ?0.5 0 20 40 60 80 3103 g24 0.5 1.0 10 30 50 70 normalized at i load = 100ma v in = 10v v out = 3.3v c ff = 12pf c out = 68f c out = 47f c out = 33f i load (ma) 0 change in v out (%) ?1.5 ?1.0 ?0.5 60 100 3103 g25 ?2.0 ?2.5 ?3.0 20 40 80 0 0.5 1.0 normalized at i load = 100ma v in = 10v v out = 1.8v c ff = 12pf c out = 100f c out = 68f c out = 47f input voltage (v) 2 85 90 100 5 7 3103 g26 80 75 3 4 6 8 9 70 65 95 maximum duty cycle (%) i out = 1ma i out = 300ma
ltc3103 7 3103f pin functions v in (pin 1): main supply pin. decouple with a 10f or larger ceramic capacitor. the capacitor should be as close to the part as possible. sw (pin 2): switch pin connects to the inductor. this pin connects to the drains of the internal main and synchronous power mosfet switches. bst (pin 3): bootstrapped floating supply for the high side gate drive. connect to sw through a 22nf (minimum) capacitor. the capacitor must be connected between bst and sw and be located as close as possible to the part as possible. gnd (pin 4): power ground. pgood (pin 5): open-drain output that is pulled to ground when the feedback voltage falls 10% (typical) below the regulation point, during a thermal shutdown event or if the converter is disabled. the pgood output is valid 1ms after the buck converter is enabled. v cc (pin 6): internally regulated supply rail. internal power rail regulated off of v in to power control circuitry. decouple with a 1f or larger ceramic capacitor placed as close to the part as possible. run (pin 7): run pin comparator input. a voltage greater than 0.84v will enable the ic. tie this pin to v in to enable the ic or connect to an external resistor divider from v in to provide an accurate undervoltage lockout threshold. 60mv of hysteresis is provided internally. fb (pin 8): feedback input to error amplifier. the resis - tor divider connected to this pin sets the buck converter output voltage. nc (pin 9): no connect pin must be tied to gnd. mode (pin 10): logic-controlled input to select mode of operation. forcing this pin high commands high ef - ficiency automatic burst mode operation where the buck will automatically transition from pwm operation at heavy load to burst mode operation at light loads. forcing this pin low commands low noise, fixed frequency, forced continuous operation. gnd (exposed pad pin 11): backpad ground common. this pad must be soldered to the pc board and connected to the ground plane for optimal thermal performance.
ltc3103 8 3103f block diagram ? + ? + + ? + uvlo i peak i peak(ref) top_on bot_on v ref_good shutdown control logic anticross conduct burst enable tsd v ref uvlo v cc osc i bias boost v cc v cc pre-reg + 0.8v run r6 r5 0.6v 0.8v ? + sd logic 7 bst v in c bst v out l1 v cc 6 mode thermal shutdown pwm comp sleep comp sleep ref gnd 0.6v ? 10% pwm ? + i peak comp ? + ? + i zero comp slope comp 0.6v ss g m c3 10 nc 9 4 3 1 sw 2 fb r2 r1 3103 bd 8 pgood 5 c2 c1
ltc3103 9 3103f operation the ltc3103 step-down dc/dc converter is capable of supplying 300ma to the load. the output voltage is adjust - able over a broad range and can be set as low as 0.6v. both the power and the synchronous rectifier switches are internal n-channel mosfets. the converter uses a constant-frequency, current mode architecture and may be configured using automatic burst mode operation for highly efficient light load operation or configured for low noise forced conduction continuous operation where the converter is optimized to operate over a broad range of step-down ratios without pulse skipping. with the auto - matic burst mode feature enabled the typical dc supply current drops to only 1.8a with no load. main control loop during normal operation, the internal top power mosfet is turned on at the beginning of each cycle and turned off when the pwm current comparator trips. the peak induc - tor current at which the comparator trips is controlled by the voltage on the output of the error amplifier. the fb pin allows the internally compensated error amplifier to receive an output feedback voltage from an external resis - tive divider from v out . when the load current increases, the output begins to fall causing a slight decrease in the feedback voltage relative to the 0.6v reference, this in turn causes the control voltage to increase until the average inductor current matches the new load current. while the top mosfet is off, the bottom mosfet is turned on until either the inductor current starts to reverse as indicated by the current reversal comparator, i zero , or the beginning of the next clock cycle. i zero is set to 40ma (typical) in automatic burst mode operation and C110ma (typical) in forced continuous mode. forced continuous mode grounding mode enables forced continuous operation and disables burst mode operation. at light loads, forced continuous mode minimizes output voltage ripple and noise but is less efficient than burst mode operation. forced continuous operation may be desirable for use in applications that are sensitive to the burst mode output voltage ripple or its harmonics. the ltc3103 offers a broad range of possible step-down ratios without pulse skipping but for very small step-down ratios, the minimum on-time of the main switch will be reached and the converter will begin turning off for multiple cycles in order to maintain regulation. burst mode operation holding the mode pin above 1.2v will enable automatic burst mode operation and disable forced continuous operation. as the load transitions current increases the converter will automatically transition between burst mode and pwm operation. conversely the converter will automatically transition from pwm operation to burst mode operation as the load decreases. between bursts the converter is not active (i.e., both switches are off) and most of the internal circuitry is disabled to reduce the quiescent current to 1.8a. burst mode entry and exit is determined by the peak inductor current and therefore the load current at which burst mode operation will be entered or exited depends on the input voltage, the output voltage and the inductor value. typical curves for burst mode entry threshold are provided in the typical performance characteristics section of this data sheet. soft-start the converter has an internal closed-loop soft-start circuit with a nominal duration of 1.4ms. the converter remains in regulation during soft-start and will therefore respond to output load transients that occur during this time. in addition, the output voltage rise time has minimal depen - dency on the size of the output capacitor or load current. thermal shutdown if the die temperature exceeds 150c (typical) the converter will be disabled. all power devices will be turned off and the switch node will be forced into a high impedance state. the soft-start circuit is reset during thermal shutdown to provide a smooth recovery once the overtemperature condition is eliminated. if enabled, the converter will restart when the die temperature drops to approximately 130c.
ltc3103 10 3103f operation power good status output the pgood pin is an open-drain output which indicates the output voltage status of the step-down converter. if the output voltage falls 10% below the regulation voltage, the pgood open-drain output will pull low. a built-in deglitch - ing delay prevents false trips due to voltage transients on load steps. the output voltage must rise 2% above the falling threshold before the pull-down will turn off. the pgood output will also pull low during overtemperature shutdown and undervoltage lockout to indicate these fault conditions. the pgood output is valid 1ms after the buck converter is enabled. when the converter is disabled the open-drain device is forced on into a low impedance state. the pgood pull-up voltage must be below the 6v absolute maximum voltage rating of the pin. current limit the peak inductor current limit comparator shuts off the buck switch once the internal limit threshold is reached. peak switch current is no less than 400ma. slope compensation current mode control requires the use of slope com - pensation to prevent sub-harmonic oscillations in the inductor current waveform at high duty cycle operation. in some current mode ics, current limiting is performed by clamping the error amplifier voltage to a fixed maximum which leads to a reduced output current capability at low step-down ratios. slope compensation is accomplished on the ltc3103 internally through the addition of a com - pensating ramp to the current sense signal. the current limiting function is completed prior to the addition of the compensation ramp and therefore achieves a peak inductor current limit that is independent of duty cycle. short-circuit protection when the output is shorted to ground, the error amplifier will saturate high and the high side switch will turn on at the start of each cycle and remain on until the current limit trips. during this minimum on-time, the inductor current will increase rapidly and will decrease very slowly during the remainder of the period due to the very small reverse voltage produced by a hard output short. to eliminate the possibility of inductor current runaway in this situation, the switching frequency is reduced to approximately 300khz when the voltage on fb falls below 0.3v. bst pin function the input switch driver operates from the voltage gener - ated on the bst pin. an external capacitor between the sw and bst pins and an internal synchronous pmos boost switch are used to generate a voltage that is higher than the input voltage. when the synchronous rectifier is on (sw is low) the internal boost switch connects one side of the capacitor to v cc replenishing its charge. when the synchronous rectifier is turned off the input switch is turned on forcing sw high and the bst pin is at a potential equal to v cc + sw relative to ground. a comparator ensures there is sufficient voltage across the boost capacitor to guarantee start-up after long sleep periods or if starting up into a pre-biased output. undervoltage lockout the ltc3103 has an internal uvlo which disables the converter if the supply voltage decreases below 2.1v (typical), the converter will be disabled. the soft-start for the converter will be reset during undervoltage lockout to provide a smooth restart once the input voltage increases above the undervoltage lockout threshold. the run pin can alternatively be configured as a precise undervoltage lockout (uvlo) on the v in supply with a resistive divider connected to the run pin.
ltc3103 11 3103f applications information the basic ltc3103 application circuit is shown as the typical application on the front page of this data sheet. the external component selection is determined by the desired output voltage, output current, desired noise im - munity and ripple voltage requirements for each particular application. however, basic guidelines and considerations for the design process are provided in this section. inductor selection the choice of inductor value influences both the efficiency and the magnitude of the output voltage ripple. larger inductance values will reduce inductor current ripple and will therefore lead to lower output voltage ripple. for a fixed dc resistance, a larger value inductor will yield higher efficiency by lowering the peak current to be closer to the average. however, a larger value inductor within the same family will generally have a greater series resistance, thereby offsetting this efficiency advantage. given a desired peak-to-peak current ripple, ? i l (a), the required inductance can be calculated via the following expression: l v out 1.2 ? ? i l ? 1? v out v in ? ? ? ? ? ? h ( ) a reasonable choice for ripple current is ?i l = 120ma which represents 40% of the maximum 300ma load current. the dc current rating of the inductor should be at least equal to the maximum load current plus half the ripple current in order to prevent core saturation and loss of efficiency during operation. to optimize efficiency the inductor should have a low series resistance. in particularly space restricted applications it may be advantageous to use a much smaller value inductor at the expense of larger ripple current. in such cases, the converter will operate in discontinuous conduction for a wider range of output loads and efficiency will be reduced. in addition, there is a minimum inductor value required to maintain stability of the current loop (given the fixed internal slope compensation). specifically, if the buck converter is going to be utilized at duty cycles greater than 40%, the inductance value must be at least l min as given by the following equation: l min 2.5 ? v out (h) table 1 depicts the minimum required inductance for several common output voltages using standard induc- tor values. table 1. minimum inductance output voltage (v) minimum inductance (h) 0.8 2.2 1.2 3.3 2.0 5.6 2.7 6.8 3.3 8.3 5.0 15 a large variety of low esr, power inductors are available that are well suited to the ltc3103 converter applications. the trade-off generally involves pcb area, application height, required output current and efficiency. table 2 provides a representative sampling of small surface mount inductors that are well suited for use with the ltc3103. the induc - tor specifications listed are for comparison purposes but other values within these inductor families are generally well suited to this application as well. within each family (i.e., at a fixed inductor size), the dc resistance generally increases and the maximum current generally decreases with increased inductance.
ltc3103 12 3103f applications information output capacitor selection a low esr output capacitor should be utilized at the buck output in order to minimize voltage ripple. multilayer ce - ramic capacitors are an excellent choice as they have low esr and are available in small footprints. in addition to controlling the output ripple magnitude, the value of the output capacitor also sets the loop crossover frequency and therefore can impact loop stability. there is both a minimum and maximum capacitance value required to ensure stability of the loop. if the output capacitance is too small, the loop crossover frequency will increase to the point where switching delay and the high frequency parasitic poles of the error amplifier will degrade the phase margin. in addition, the wider bandwidth produced by a small output capacitor will make the loop more sus - ceptible to switching noise. at the other extreme, if the output capacitor is too large, the crossover frequency can decrease too far below the compensation zero and also lead to degraded phase margin. table 3 provides a guideline for the range of allowable values of low esr output capacitors assuming a feedforward capacitor is used. see the output voltage programming section for details on selecting a feedforward capacitor. larger value output capacitors can be accommodated provided they have sufficient esr to stabilize the loop, or by increasing the value of the feedforward capacitor in parallel with the upper resistor divider resistor. in burst mode operation, the output capacitor stores energy to satisfy the load current when the ltc3103 is in a low current sleep state between the burst pulses. it can take several cycles to respond to a large load step during a sleep period. if large transient load currents are required then a larger capacitor can be used at the output to minimize output voltage droop until the part transitions from burst mode operation to continuous mode operation. note that even x5r and x7r type ceramic capacitors have a dc bias effect which reduces their capacitance when a dc voltage is applied. it is not uncommon for capacitors offered in the smallest case sizes to lose more than 50% of their capacitance when operated near their rated volt - age. as a result it is sometimes necessary to use a larger capacitance value or use a higher voltage rating in order to realize the intended capacitance value. consult the manu - facturers data for the capacitor you select to be assured of having the necessary capacitance in your application. table 3. recommended output capacitor limits output voltage (v) c min (f) c max (f) 0.8 22.0 220 1.2 15.0 220 2.0 12.0 100 2.7 6.8 68 3.3 4.7 47 5.0 4.7 47 table 2. representative inductor selection part number value (h) dcr () max dc current (a) size (mm) w l h coilcraft epl3015 6.8 0.19 1.00 3.0 3.0 1.5 lps3314 10 0.33 0.70 3.3 3.3 1.3 lps4018 15 0.26 1.12 4.0 4.0 1.8 cooper-bussman sd3114 6.8 0.30 0.98 3.1 3.1 1.4 sd3118 10 0.3 0.75 3.2 3.2 1.8 murata lqh3npn 6.8 0.20 1.25 3.0 3.0 1.4 lqh44pn 10 0.16 1.10 4.0 4.0 1.7 sumida cdrh3d16 6.8 0.17 0.73 3.8 3.8 1.8 cdrh3d16 10 0.21 0.55 3.8 3.8 1.8 taiyo-yuden cbc3225 6.8 0.16 0.93 3.2 2.5 2.5 nr3015 10 0.23 0.70 3.0 3.0 1.5 nr4018 15 0.30 0.65 4.0 4.0 1.8 wrth 744029006 6.8 0.25 0.95 2.8 2.8 1.4 744031006 6.8 0.16 0.85 3.8 3.8 1.7 744031100 10 0.19 0.74 3.8 3.8 1.7 744031100 15 0.26 0.62 3.8 3.8 1.7 panasonic ellvgg6r8n 6.8 0.23 1.00 3.0 3.0 1.5 ell4lg100ma 10 0.20 0.80 3.8 3.8 1.8 tdk vlf3012 6.8 0.18 0.78 3.0 2.8 1.2 vlc4018 10 0.16 0.85 4.0 4.0 1.8
ltc3103 13 3103f input capacitor selection the v in pin provides current to the power stages of the buck converter. it is recommended that a low esr ceramic capacitor with a value of at least 10f be used to bypass the pin. these capacitors should be placed as close to the pin as possible and should have a short return path to the gnd pin. output voltage programming the output voltage is set by a resistive divider according to the following formula: v out = 0.6v ? 1 + r2 r1 ? ? ? ? ? ? the external divider is connected to the output as shown in figure 1. note that fb divider current is not included in the ltc3103 quiescent current specification. for improved transient response, a feedforward capacitor, c ff , may be placed in parallel with resistor r2. the capacitor modifies the loop dynamics by adding a pole-zero pair to the loop dynamics which generates a phase boost that can improve the phase margin and increase the speed of the transient response, resulting in smaller voltage deviation on load transients. the zero frequency depends not only on the value of the feed forward capacitor, but also on the upper resistor divider resistor. specifically, the zero frequency, f zero , is given by the following equation: f zero = 1 2 ? ? r2 ? c ff1 for r2 resistor values of ~1m a 12pf ceramic capacitor will suffice, however that value may be increased or de - creased to optimize the converters response for a given set of application parameters. minimum off-time/on-time considerations the maximum duty cycle is limited in the ltc3103 by the boost capacitor refresh time, the rise/fall times of the switch as well as propagation delays in the pwm comparator, the level shifts and the gate drive. this minimum off time is typically 65ns which imposes a maximum duty cycle of: dc max = 1 C (f ? t off(min) ) where f is the 1.2mhz switching frequency and t off(min) is the minimum off-time. if the maximum duty cycle is surpassed, due to a dropping input voltage for example, the output will drop out of regulation. the minimum input voltage to avoid this dropout condition is: v in(min) = v out 1? f ? t off(min) ( ) conversely, the minimum on-time is the smallest duration of time in which the buck switch can be in its on state. this time is limited by similar factors and is typically 70ns. in forced continuous operation, the minimum on-time limit imposes a minimum duty cycle of: dc min = f ? t on(min) where t on(min) is the minimum on-time. in extreme step- down ratios where the minimum duty cycle is surpassed, the output voltage will still be in regulation but the rectifier switch will remain on for more than one cycle and sub- harmonic switching will occur to provide a higher effective duty cycle. the result is higher output voltage ripple. this is an acceptable result in many applications so this constraint may not be of critical importance in some cases. precise undervoltage lockout the ltc3103 is in shutdown when the run pin is low and active when the pin is higher than the run pin threshold. the rising threshold of the run pin comparator is an accurate 0.8v, with 60mv of hysteresis. this threshold is enabled when v in is above the 2.5v minimum value. if v in is lower than 2.5v, an internal undervoltage monitor puts the part in shutdown independent of the run pin state. the run pin can be configured as a precise undervoltage lockout (uvlo) on the v in supply with a resistive divider fb r2 r1 c ff 3103 f01 v out gnd ltc3103 figure 1. setting the output voltage applications information
ltc3103 14 3103f tied to the run pin as shown in figure 2 to meet specific v in voltage requirements. if used, note that the external divider current is not included in the ltc3103 quiescent current specification. the rising uvlo threshold can be calculated using the following equation: v uvlo = 0.8v ? 1 + r4 r3 ? ? ? ? ? ? applications information internal v cc regulator the ltc3103 uses an internal nmos source follower regulator off of v in to generate a low voltage internal rail, v cc . the regulator is designed to deliver current only to the internal drivers and other internal control circuits and not to an external load. the v cc pin should be bypassed with a 1f or larger ceramic capacitor. boost capacitor selection the ltc3103 uses a bootstrapped supply to power the buck switch gate drivers. when the synchronous rectifier turns on, an internal pmos switch turns on synchronously to charge the boost capacitor, c bst , to the voltage on v cc . for most applications a 0.022f will suffice. the capaci - tor should be placed as close to their respective pins as possible. figure 3. pcb layout recommendations 10 9 6 7 8 4 5 3 2 1 mode nc fb run v cc v in sw bst gnd pgood kelvin to v out 3103 f03 uninterrupted ground plane should exist under all components shown and under the traces connecting those components v out via ground plane v in run ltc3103 gnd v in r3 r4 3103 f02 figure 2. setting the undervoltage lockout threshold
ltc3103 15 3103f typical applications v in c bst 0.022f bst v in 5v to 9v mode sw run pgood pgood v cc fb ltc3103 gnd r1 442k l1 10h v out 3.3v 300ma 1m 3103 ta02a 47f l1: tdk vlc4018 1f 10f r2 2m c ff 12pf portable lf rfid reader, dual lithium-ion to 3.3v/300ma regulator with ultralow i q efficiency vs output current 12v to 2.2v/300ma regulator with 9v accurate uvlo start-up with ramped input power v in c bst 0.022f bst v in 12v mode sw run pgood pgood v cc fb ltc3103 gnd r1 665k r4 2.05m r3 200k l1 10h v out 2.2v 300ma 1m 3103 ta03a 47f l1: murata lqh44pn1 1f 10f r2 1.78m c ff 12pf load current (a) 80 efficiency (%) 90 100 70 85 95 0.0001 0.01 0.1 1 3103 ta02b 60 75 65 0.001 v in = 5v v in = 9v v out 1v/div v in 5v/div i l 100ma/div 20ms/div 3103 ta03b
ltc3103 16 3103f typical applications slolar-powered 2.2v supply with li battery backup and run threshold set to battery minimum voltage v in c bst 22nf bst mode sw run pgood v cc fb ltc3103 gnd r1 665k r4 3.09m sdm20e-40c r3 715k l1 15h v out 2.2v 3103 ta04 c out 22f c1 1f l1: coilcraft lp54018 c in 10f c bulk 100f 3.6v tadiran aa lithium battery r2 1.78m c ff 22pf 3.2v run threshold + 4.8v, 0.5w solar panel mpt4.8-150 (6.5voc) + +
ltc3103 17 3103f typical applications 5v to 1.2v/300ma low noise regulator using forced continuous operation efficiency vs output current v in c bst 0.022f bst v in 5v mode sw run pgood pgood v cc fb ltc3103 gnd r1 402k l1 4.7h v out 1.2v 300ma 1m 3103 ta05a 10f l1: sumida cdrh4d11np-4r7n 1f 10f on off r2 402k c ff 22pf output current (a) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.0001 0.01 0.1 1 3103 ta05b 0 0.001 v in = 2.5v v in = 3.3v v in = 5v
ltc3103 18 3103f dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699 rev c) 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.125 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dd) dfn rev c 0310 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.70 0.05 3.55 0.05 package outline 0.25 0.05 0.50 bsc pin 1 notch r = 0.20 or 0.35 45 chamfer package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
ltc3103 19 3103f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. msop (mse) 0911 rev h 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ? 0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 1 2 3 4 5 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8910 10 1 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 1.68 0.102 (.066 .004) 1.88 0.102 (.074 .004) 0.50 (.0197) bsc 0.305 0.038 (.0120 .0015) typ bottom view of exposed pad option 1.68 (.066) 1.88 (.074) 0.1016 0.0508 (.004 .002) detail ?b? detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.05 ref 0.29 ref mse package 10-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1664 rev h) package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
ltc3103 20 3103f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2011 lt 1111 ? printed in usa related parts typical application 12v to 5v/300ma regulator with high efficiency, ultralow i q (1.8a with v out in regulation, no load) v in c bst 0.022f bst v in 12v mode sw run pgood v cc fb ltc3103 gnd r1 255k l1 10h v out 5v 300ma 1m pgood 3103 ta06 47f l1: sumida cdrh4d16fb 1f 10f r2 1.87m c ff 10pf part number description comments ltc3104 15v, 300ma synchronous step-down dc/dc converter with ultralow quiescent current and 10ma ldo v in : 2.5v to 15v, v out(min) = 0.6v, i q = 2.8a, i sd = 1a, 3mm 3mm dfn-10, msop-10 ltc3642 45v (transient to 60v) 50ma synchronous step-down dc/dc converter v in : 4.5v to 45v, v out(min) = 0.8v, i q = 12a, i sd < 1a, 3mm 3mm dfn-8, msop-8 ltc3631 45v (transient to 60v) 100ma synchronous step-down dc/dc converter v in : 4.5v to 45v, v out(min) = 0.8v, i q = 12a, i sd < 1a, 3mm 3mm dfn-8, msop-8 ltc3632 50v (transient to 60v) 20ma synchronous step-down dc/dc converter v in : 4.5v to 50v, v out(min) = 0.8v, i q = 12a, i sd < 1a, 3mm 3mm dfn-8, msop-8 ltc3388-1/ltc3388-3 20v, 50ma high efficiency nano power step-down regulators v in : 2.7v to 20v, v out(min) fixed 1.1v to 5.5v, i q = 720na, i sd = 400na, 3mm 3mm dfn-10, msop-10 ltc3108/ltc3108-1 ultralow voltage step-up converter and power managers v in : 0.02v to 1v, v out(min) fixed 2.35v to 5v, i q = 6a, i sd < 1a, 3mm 4mm dfn-12, ssop-16 ltc3109 auto-polarity, ultralow voltage step-up converter and power manager v in : 0.03v to 1v, v out(min) fixed 2.35v to 5v, i q = 7a, i sd < 1a, 4mm 4mm qfn-20, ssop-20 ltc4071 li-ion/polymer shunt battery charger system with low battery disconnect charger plus pack protection in one ic low operating current (550na), 50ma internal shunt current, pin selectable float voltages (4.0v, 4.1v, 4.2v), 8-lead, 2mm 3mm, dfn and msop packages ltc4070 li-ion/polymer low current shunt battery charger system selectable v float = 4.0v, 4.1v, 4.2v, max shunt current = 50ma, i ccq = 450na to 1.04ma, i ccqlb = 300na, 2mm 3mm dfn-8, msop-8 ltc1877 10v, 600ma high efficiency synchronous step-down dc/dc converter v in : 2.65v to 10v, v out(min) = 0.8v, i q = 10a, i sd < 1a, msop-8 ltc3105 5v, 400ma, mppc step-up converter with 250mv start-up v in : 0.225v to 5v, v out(max) = 5.25v, i q = 24a, i sd = 10a, 3mm 3mm dfn-10, msop-12

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